Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same, which include a buried gate region, a nitride film spacer over sidewalls of the buried gate region, and a spacer in an active region etched in such a manner that a spacer remains in a device isolation region. As a result, even if a void occurs in the device isolation region, the spacer can prevent the occurrence of short-circuiting between the device isolation region and its neighboring gates.
A semiconductor memory device includes a plurality of unit cells each having a capacitor and a transistor. The capacitor is used to temporarily store data, and the transistor is used to transfer data between a bit line and the capacitor in response to a control signal (word line). The data transfer occurs using a semiconductor property where electrical conductivity changes depending on the environment. The transistor has three regions, i.e., a gate, a source, and a drain. Electric charges move between the source and the drain according to a control signal inputted to the gate of the transistor. The movement of the electric charges between the source and the drain is achieved through a channel region.
When a general transistor is formed on a semiconductor substrate, a gate may be formed on the semiconductor substrate and impurities may be doped into both sides of the gate so as to form a source and a drain. As the data storage capacity of a semiconductor memory device has increased and the feature width thereof has decreased, the size of each unit cell must be gradually decreased. That is, the design rule of the capacitor and the transistor included in the unit cell has been reduced. Thus, as the channel length of a cell transistor is gradually decreased, the short channel effect, Drain Induced Barrier Lower (DIBL), etc. occur in the general transistor and thus operational reliability deteriorates. By maintaining a threshold voltage such that the cell transistor performs a normal operation, it is possible to solve the phenomena generated due to decreased channel length. In general, as the channel of the transistor shortens, the concentration of the impurities doped into a region in which the channel is formed may be increased.
However, if the concentration of the impurities doped into the channel region is increased while the design rule is reduced to 100 nm or less, the electric field of a Storage Node (SN) junction is increased, thereby lowering the refresh characteristics of the semiconductor memory device. In order to solve this problem, a cell transistor having a three-dimensional channel structure, in which the channel extends in a vertical direction, is so that the channel length of the cell transistor can be maintained even when the design rule is decreased. That is, even when a channel width in a horizontal direction is short, since the channel length of a vertical direction is secured, the impurity doping concentration may be reduced, thus preventing refresh characteristics from being lowered.
In addition, as the integration degree of the semiconductor device is increased, the distance between a word line coupled to a cell transistor and a bit line coupled to the cell transistor is gradually reduced. As a result, shortcomings may arise in which parasitic capacitance is increased such that an operation margin of a sense amplifier (sense-amp), which amplifies data transmitted via the bit line, is deteriorated. This negatively influences the operational reliability of the semiconductor device. In order to solve the above-mentioned shortcomings while simultaneously reducing parasitic capacitance between a bit line and a word line, a buried word line structure has been proposed recently in which a word line is formed only in a recess instead of an upper part of the semiconductor substrate. The buried word line structure includes a conductive material in a recess formed in a semiconductor substrate. An upper part of the conductive material is covered with an insulation film such that the word line is buried in a semiconductor substrate. As a result, the buried word line structure can be electrically isolated from a bit line formed over a semiconductor substrate including source/drain regions.
However, the buried word line (buried gate) structure has some disadvantages. First, Gate Induced Drain Leakage (GIDL) characteristics occur between a conductive material (gate electrode) and an N-type junction of an active region. Second, refresh characteristics of the whole semiconductor device deteriorate due to the GIDL characteristics.
FIG. 1 is a plan view illustrating a semiconductor device according to the related art.
Referring to FIG. 1, a device isolation region 120 defining an active region 110, and a buried gate 140 crossing the active region 110 are formed over a semiconductor device 100. In this case, the active region 110 is formed as an island type, a nitride seam 130 or void caused due to a poor gap-filling characteristic occurs in the device isolation region 120 between neighboring active regions 110. When depositing tungsten (W) to form a buried gate in a subsequent process, the seam 130 or void is filled with tungsten W, such that a bridge may occur between the buried gates 140 or an inter-cell leakage may also occur.